1. Technical Field
The present invention relates generally to a semiconductor memory device, and more particularly to a reading method of a nonvolatile memory device.
2. Related Art
In general, a semiconductor memory device is classified into a volatile memory device and a nonvolatile memory device. The volatile memory device loses data stored therein when power supply is interrupted or switched off, but the nonvolatile memory device maintains data stored therein even in absence of power supply.
There are various types of nonvolatile memory devices. The nonvolatile memory device may be divided into a flash memory device, a ferroelectric RAM (FRAM) using a ferroelectric capacitor, a magnetic RAM (MRAM) using a tunneling magneto-resistive (TMR) layer, a phase change memory device using chalcogenide alloys and the like.
Among the nonvolatile memory devices, the flash memory device is roughly divided into a NOR flash memory device and a NAND flash memory device, depending on the configuration of memory cells and bit lines. The NOR flash memory device has a structure in which two or more memory cell transistors are coupled in parallel to one bit line. Therefore, the NOR flash memory device has an excellent random access time characteristic. On the other hand, the NAND flash memory device has a structure in which two or more memory cell transistors are coupled in series to one bit line. Such a structure is referred to as a cell string, and one bit line contact is required per one cell string. Therefore, the NAND flash memory device has an excellent characteristic in terms of integration degree.
The semiconductor memory device such as the NAND flash memory device may include a multi-level cell (MLC) capable of storing two or more-bit data per memory cell to increase the storage capacity. For example, an MLC to store two-bit data may store two bits of the most significant bit (MSB) and the least significant bit (LSB).
In a read operation for the MLC, a flag cell may be used to quickly perform the read operation. The flag cell stores information on whether the MSB was programmed in the MLC or not. According to whether the flag cell was programmed or not, the read operation algorithm of the NAND flash memory device may vary. For example, when it is determined that the flag cell was not programmed, the read operation for the MSB may be omitted. On the other hand, when it is determined that the flag cell was programmed, the read operation for the MSB may be normally performed.
In order to quickly perform the read operation of the NAND flash memory device, an operation of checking the state of the flag cell is performed. In some cases, however, a read operation for checking the state of the flag cell may be added. In this case, the added read operation may serve as a factor which degrades the read performance of the NAND flash memory device.